The present invention relates to a semiconductor integrated circuit which can operate at high speed and is highly integrated, and more particularly to a large-capacity, high-speed dynamic random access memory (DRAM).
As the capacity of a semiconductor integrated circuit increases, the load capacitance thereof is usually increased, and thus the charge/discharge time of the load capacitance is also increased. Further, as the integration density of the semiconductor integrated circuit increases, the width and thickness of metal wiring are reduced, and thus the wiring resistance of a signal line is increased. Such an increase in wiring resistance furthers the above increase in charge/discharge time. Accordingly, it is indispensable for the realization of an ultra large scale integration circuit that reduction of the load capacitance or wiring resistance per one signal line must be achieved, thereby increasing an operation speed.
It is important for the high-speed operation of a dynamic random access memory (DRAM) to reduce the charge/discharge time associated with each of the data lines and which data lines characteristically produce the greater part of the load capacitance. One prior technique for reducing the charge/discharge time of data line is disclosed in a Japanese Patent Application JP-A-sho62-107,497 (corresponding to U.S. Pat. No. 4,796,234). According to this technique, the load capacitance of a transistor for driving a group of sense amplifiers is reduced to one-half of an ordinary value. Accordingly, the charge/discharge time of a data line can be reduced to one-half of an ordinary value. However, with an increase in capacity of the DRAM, the load capacitance and the wiring resistance are further increased. Accordingly, it will become difficult in future instances to maintain the high-speed operation of the DRAM only by employing the above technique. In addition, in order to cope with a reduction in breakdown voltage of a circuit element resulting from an increase in integration of the DRAM and an increase in power consumption which, in turn, results from an increase in capacity thereof, an operating voltage associated therewith would be reduced. As a result, the operating voltage would remain close to the threshold voltage of each of MOSFETs making up a sense amplifier. Thus, there will arise a problem that the driving ability of the sense amplifier would become reduced and the high-speed performance thereof would be degraded substantially.
As the capacity of a DRAM is increased, a bit width (namely, the number of I/Os which are accessible at the same time) is usually increased from 1 or 4 bits to 8 bits (namely, byte width), 16 bits, or 32 bits. Accordingly, it is important to increase the number of input/output lines for transferring data between a memory array and an input/output circuit. Further, in order to cope with a substantial increase of test time resulting from an increase in integration of a DRAM, a highly-integrated DRAM is required to have a parallel test function. An example of the parallel test function is described on pages 240 and 241 of the Digest of Technical Papers ISSCC, 1985. It is important for such a parallel test to increase the number of input/output lines for transferring multi-bit data at once between a memory array and a peripheral circuit. In a conventional integrated circuit, however, the layout of, for example, a DRAM is arranged so that the input/output lines reach a sense amplifier. Accordingly, there arises a problem that an increase of the number of input/output lines correspondingly brings about an increase in the layout of the DRAM area.
As mentioned above, according to the prior art, it would be difficult to cope with an increase in charge/discharge time resulting from a substantial increase of load capacitance and wiring resistance that would be attributed to ultra LSI of the future. Further, it would also be difficult to increase a data bit width.